1. Field of the Invention
The present invention relates generally to memory devices and, more particularly, to devices implemented to synchronize signals in memory devices.
2. Description of the Related Art
This section is intended to introduce the reader to various aspects of art which may be related to various aspects of the present invention which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
In high speed memory devices such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) devices, it is often desirable to synchronize the timing of certain signals, such as clock signals and data signals which may be external to the memory devices, with internally generated clock signals or data signals, or with other external signals. Various synchronization devices may be implemented to provide an output signal that is matched in terms of frequency and/or phase to the input signal, which may be an external clock signal, for example. Synchronization devices may, for example, be implemented to synchronize an external system clock with data being transmitted from the memory device. Ideally, the time between the transition of the clock signal and the edge of the data signal (i.e., the “access time”) is zero. Accordingly, it is advantageous to minimize the access time (tAC) in memory devices.
Synchronization devices, such as delay locked loop (DLL) circuits, measure controlled delay (MCD) circuits and synchronous mirror delay (SMD) circuits, for example, implement I/O modeling techniques to mimic actual input/output (I/O) delay paths in the memory device such that the input signal can be shifted to account for the delays. Accordingly, synchronization devices are generally designed under an assumption that the I/O model properly mimics the actual I/O delay paths. Disadvantageously, if the I/O model does not properly mimic the actual I/O delay path, a synchronization device may not maintain proper access time (tAC) across all device voltages and temperatures that may be experienced during device operation. Accordingly, it may be advantageous to provide synchronization devices that can be tuned to provide a delay that behaves with a desired delay response across VDD and temperature.
Embodiments of the present invention may address one or more of the problems set forth above.